There are many different types of memory used to store data. One type of memory is Electrically Erasable Programmable Read-Only Memory (EEPROM), which is used in many electronic products (e.g., to store calibration and customer specific data for industrial and automotive sensors). FIG. 1 shows a circuit schematic for a conventional EEPROM memory cell 100. The EEPROM memory cell 100 includes a first transistor 102 (e.g., typically an NMOS transistor) having a capacitor 104 coupled to its gate. A first plate of the capacitor (tied to a gate of the first transistor) can be referred to as a floating gate (FG), while a second plate of the capacitor can be referred to as a control gate (CG).
To write to the memory cell 100, voltages can be selectively applied to the control gate CG to add charge or subtract charge from the floating gate FG, thereby programming the memory cell to a desired data state. Because the floating gate FG is electrically isolated, any charge placed on the floating gate is trapped there and will remain there for an extended time period (e.g., years) or until it is removed by writing another data state to the cell. Thus, EEPROM cells are said to be non-volatile, because the data contents remain there even if power is disconnected from the cell.
For example, to write a first data state to the memory cell (e.g., a logical “1”), a relatively large voltage (e.g., 21 V for tunneling oxide thicknesses around 15 nm) can be applied to the control gate CG relative to the body of the first transistor 102 (e.g., held at 0V), thereby resulting in a predetermined amount of charge (e.g., electrons) being “trapped” on the floating gate FG via Fowler-Nordheim tunneling, for example. These electrons can decrease the electrical potential of the floating gate FG, for example, such that the potential of the FG is lower than a threshold voltage of the first transistor 102. Conversely, to write a second data state to the memory cell (e.g., a logical “0”), a relatively small voltage (e.g., 0V) can be applied to the control gate CG relative to the body of the first transistor (e.g., held at 21V), thereby removing electrons from the floating gate FG and increasing its potential to be higher than that of the voltage threshold of the first transistor 102. Also a negative voltage (e.g. −21V) can be applied to the control gate relative to the body of the first transistor in order to write a second data (e.g., a logical “0”).
When the cell 100 is subsequently read, a suitable read bias is applied to a second transistor 106 also called the select transistor (e.g., NMOS transistor) to turn the second transistor on. The amount of current, if any, flowing over the second transistor 106 corresponds to the charge previously stored on the floating gate FG. For example, if a logical “1” is stored in the cell in our example (which corresponds to the potential of FG being less than the voltage threshold of the first transistor 102), a limited amount of current (almost no current or extremely low leakage current) will flow because the first transistor 102 is effectively “off”. By contrast, if a logical “0” is stored in the cell 100 in our example (which corresponds to the potential of FG being greater than the voltage threshold of the first transistor 102), a significant amount of current will flow because the transistor 102 is “on”. Thus, by measuring the current output, the state of the cell 100 can be determined. In other embodiments, voltages rather than currents could be used to measure the state of the cell.
In any case, one shortcoming of this conventional EEPROM cell 100 is that it may require a first voltage (e.g. 21V) to erase the memory cell (e.g., write a logical “0” to the cell), and a second, different voltage (e.g., 19V) to program the memory cell (e.g., write a logical “1” to the cell) in order to guarantee the same voltages induced on FG during programming and erasing, or in other words, in order to guarantee the same coupling factor. To achieve these different voltages, the memory device requires a voltage divider or similar circuitry. In addition to requiring area on the chip (area corresponds to cost in many respects), this circuitry also may consume additional power. Therefore, to reduce costs and power requirements, the inventors have appreciated that it would be beneficial to use the same voltage to program and erase each memory cell. However, until now, using the same voltage for program and erase operations would provide unnecessary stress on the first transistor 102 (e.g., a tunneling oxide of the first transistor) during programming and even cause it to breakdown in the worst case.
Therefore, the inventors have devised techniques by which the same voltage can be used for program and erase operations while at the same time limiting the stress incurred by the features of the memory cell. In addition, a kind of universal EEPROM cell can be created, where a desired voltage across the tunneling oxide can be controlled/adjusted in an electronic way.